Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing

We propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-ofproducts expression, divides and recombines the product terms. gradually progressing toward a minimal solution. The input expression can be user-specijied or one produced by another heuristic. Unlike recently studied minimization techniques (which are classijied as direct-cover methodr). our technique manipulates product terms directly, breaking them up and joining them in different ways while reducing the total number of product terms. We show two mechanisms for recombining product terms and compare the results with presently known heuristics. A benefit of simulated annealing is that improved solutions can be achieved by increasing computation time.